This invention relates, in general, to high voltage protection circuitry for an integrated circuit, and more particularly, to electrostatic discharge (ESD) protection of an integrated circuit.
An integrated circuit is typically one element of a larger system comprising many circuits. Interconnection between integrated circuits takes many forms. For example, an integrated circuit is placed in a package where wire is bonded between the metal pads of the integrated circuit and leads of the package. The leads of the package typically couple to an integrated circuit board or integrated circuit socket. A high density interconnect format places solder balls on each metal pad of the integrated circuit. The integrated circuit is connected via the solder to corresponding metal pads on another substrate. In either case, the metal pads of an integrated circuit are the interface circuitry between circuitry external to the integrated circuit and circuitry internal to the integrated circuit.
It is inevitable that an integrated circuit is handled after wafer processing, during testing, packaging, and when placed in a system. Any handling of the integrated circuit exposes the device to an electrostatic discharge. Reliability and premature failure of an integrated circuit are a consequence of ESD. An ESD event produces extremely high voltages that can damage devices of the integrated circuit.
The pads or connection points are the pathway to circuitry internal to an integrated circuit. An ESD event applied to a pad couples a voltage typically exceeding a thousand volts to circuitry connected to the pad. The first circuit typically connected to a pad is either an Input or Output circuit. In general, an ESD event damages the Input/Output (I/O) circuitry if it is not protected by ESD protection circuitry. An ESD event is indiscriminate in its entry to the integrated circuit. The ESD event can be coupled to any I/O circuit of the integrated circuit or between I/O circuits of the integrated circuits.
In general, ESD protection circuitry is incorporated near the pad areas of an integrated circuit. The ESD protection circuitry dissipates an ESD event before harmful voltages or currents can damage circuitry of the integrated circuit. A problem with ESD protection circuitry is the protection mechanism is not reliable over all operating conditions. Both the breakdown mechanism (due to an ESD event) of a device in the I/O circuitry and the point at which the ESD protection circuitry is enabled is an important point of consideration in the development of an ESD circuit.
Another design factor in an ESD protection circuit is the area it takes up near a pad. Many integrated circuits are pad limited due to the high density available in today's integrated circuit processes. A high density ESD protection circuit would help in reducing die area and increasing pad density.
A further factor in ESD protection is the particular application of the device or circuitry to be protected. For example, a critical parameter for all radio frequency (RF) applications is sensitivity. Due to this sensitivity, RF I/O circuits either eliminate ESD protection or limit the protection to minimally acceptable levels to avoid the capacitance that is added to any circuit when adding additional devices and which adversely affects the sensitivity. However with RF applications becoming prevalent in the consumer market, to minimize costs such as actual circuit loss and subsequent board rework, ESD robustness for RF circuitry is a must.
It would be of great benefit if an ESD protection circuit could be provided that is easily manufacturable and provides protection from most ESD events that can occur on an integrated circuit. It would be of further benefit if an ESD protection circuit could be provided for RF applications.